45.8.19

Table 45-20. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CryptoMaster_DMA_Registers__STATUS
Offset: 0x1003C
Reset: 0x00000000
Property: R

Bit 3130292827262524 
 PUSH_NBDATA[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 PUSH_NBDATA[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  SOFT_RST_BUSYPUSH_WAITINGFIFOFETCH_NOT_EMPTY  PUSH_BUSYFETCH_BUSY 
Access RRRRR 
Reset 00000 

Bits 31:16 – PUSH_NBDATA[15:0] Pusher Number of Data

Number of data in output FIFO (pusher)

Bit 6 – SOFT_RST_BUSY Soft Reset Busy

This bit is high when the soft reset is “on going”

Bit 5 – PUSH_WAITINGFIFO Pusher Waiting FIFO

This bit is high when the pusher if waiting for more data

in output FIFO.

Bit 4 – FETCH_NOT_EMPTY Flag

Not empty flag from input FIFO (fetcher)

Bit 1 – PUSH_BUSY Pusher busy

This bit is high as long as the pusher is busy.

Bit 0 – FETCH_BUSY Fetcher busy

This bit is high as long as the fetcher is busy.