45.8.18
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CryptoMaster_DMA_Registers__CONFIG |
| Offset: | 0x10034 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SOFT_RST | PUSH_STOP | FETCH_STOP | PUSH_CTRL_INDIRECT | FETCH_CTRL_INDIRECT | |||||
| Access | RW | RW | RW | RW | RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – SOFT_RST Software reset
When this bit is high, the software reset of the DMA modules, the FIFO’s and the processing module will be activated. The AXI bus is not affected (pending transfers will be completed).
Bit 3 – PUSH_STOP Stop pusher
When this bit is high, the pusher will stop at the end of the current block (even if the STOP bit in the descriptor is low).
Bit 2 – FETCH_STOP Stop fetcher
When this bit is high, the fetcher will stop at the end of the current block (even if the STOP bit in the descriptor is low).
Bit 1 – PUSH_CTRL_INDIRECT Pusher scatter/gather
When this bit is zero, the pusher runs in direct mode.
When this bit is one, the pusher runs in scatter-gather mode.
Bit 0 – FETCH_CTRL_INDIRECT Fetcher scatter/gather
When this bit is zero, the fetcher runs in direct mode.
When this bit is one, the fetcher runs in scatter-gather mode.