4.3.1.1 Reference Clock Inputs

PLLs have two reference clock inputs (REF_CLK_0 and REF_CLK_1) and support dynamic clock switching. The REF_CLK_1 acts as a backup clock and must be operated at the same frequency as REF_CLK_0 but sourced from a different clock source. The reference clock frequency ranges from 1 MHz to 1250 MHz in integer mode, and 10 MHz to 1250 MHz in fractional mode. A stable reference clock must be supplied to the PLL. The POWERDOWN_N input can be used to keep the PLL in reset until the reference clock is stable.

If the reference clock is sourced from an external source through an I/O, then the PLL must be held in power-down state from the fabric logic until the input buffer of the I/O is known to be operational. This is when the later of the following two conditions occur:

  • FABRIC_POR_N negates
  • BANK_y_VDDI_STATUS asserts (where y is the number of the I/O bank containing the input buffer). Use the PF_INIT_MONITOR macro to get the status of an I/O bank and FABRIC_POR_N.

If the reference clock is sourced from the on-chip oscillator, then connect the POWERDOWN_N input to FABRIC_POR_N.

The reference clock must be sourced from one of the following:

  • Preferred clock inputs
  • High-speed I/O clocks
  • FPGA fabric routed clocks
  • Transceiver reference clocks (to CCC_SE only)
  • Transceiver interface clocks (to CCC_SE and CCC_NE)
Important: The preferred clock inputs which are capable of driving CCCs have dedicated connections to clock inputs (reference clock or feedback clock) of PLLs and/or DLLs present in the CCCs. For the connectivity of preferred clock inputs to PLLs and DLLs present in a CCC, see Preferred Clock Inputs Connectivity in CCCs.

The clock switching feature is useful in applications that require a redundant reference clock when the primary reference clock stops running. The control signal (REF_CLK_SEL) for the clock switching comes from the FPGA fabric and it must be driven by the user logic to initiate clock switching.

  • When REF_CLK_SEL = 1, the PLL selects REF_CLK_1 as the reference clock.
  • When REF_CLK_SEL = 0, the PLL selects REF_CLK_0 as the reference clock.

The selected reference clock is passed through a reference divider (RFDIV) before it is fed into the Phase Frequency Detector (PFD). The division values for RFDIV range from 1 to 63. The valid operating range of PFD input frequency (FPFD) is 1 MHz to 312 MHz in integer mode, and 10 MHz to 250 MHz in fractional mode.

Figure 4-4. PLL Block Diagram—Clock Inputs and Outputs