4.3.1.8 Bandwidth Adjustment

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PLL loop bandwidth is the measure of the PLL's ability to track the reference clock and its jitter. The PLL filters the jitter present above the loop bandwidth. PLL passes the jitter (aka wander) below the loop bandwidth. PLLs provide a programmable bandwidth feature, which is configurable using the CCC configurator. The following table lists bandwidth parameter settings.

If the reference clock has a significant amount of jitter, use lower bandwidth to filter the noise. If a higher quality reference clock is used, fast lock time is achieved by using a higher bandwidth value. The CCC Configurator displays the computed bandwidth value based on the PLL bandwidth parameter configuration. For PLL jitter performance, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .

Note: In the respective PolarFire Device Register Map, PolarFire SoC Register Map, or RT PolarFire SoC Register Map (will be available in a future release), on the PLL tab, the BWP field of the PLL_CTRL2 register (Proportional Path loop bandwidth control) controls the loop bandwidth. The BWP field is mapped to the configurator as shown in the following table.

Table 4-3. PLL Bandwidth Parameter Settings
Bandwidth Settings	BWP Field Value	Description
Low	0x00	PLL with a low bandwidth; has better jitter rejection, but a slower lock time.
Medium-Low	0x01	PLL with a bandwidth between low to medium; has a balance between lock time and jitter rejection. This is the recommended setting.
Medium-High	0x10	PLL with a bandwidth between medium to high.
High	0x11	PLL with a high bandwidth; has a faster lock time but tracks more jitter.