4.3.1.2 Feedback Clock Input

The feedback clock input (FB_CLK) is available only when a PLL is configured in external feedback mode. The PLL clock output 0 must be connected to FB_CLK.

The preferred clock inputs which are capable of driving CCCs have dedicated connections to clock inputs (reference clock or feedback clock) of PLLs and/or DLLs present in the CCCs. For the connectivity of preferred clock inputs to PLLs and DLLs present in a CCC, see Preferred Clock Inputs Connectivity in CCCs.

Each PLL has a feedback divider (FBDIV), and a delta-sigma modulator in the feedback path for fractional frequency generation. The division values for FBDIV range from 8 to 10 and 12 to 4095 in integer mode, and 20 to 500 in fractional mode. The FBDIV (INTIN) represents the integer part of the PLL feedback value in fractional mode. The fractional part (FRAC/FRACIN) of the PLL feedback divide value is controlled by the delta-sigma modulator with 24-bit resolution. Total feedback divide value is equal to (FBDIV + FRAC/2^24).