9.10.6 CAN Clock Control Register

Note:

The user must ensure the input clock source is 640 MHz or less. Operation with an input reference frequency above 640 MHz will result in unpredictable behavior.
The CANCLKDIVx divider value must not be changed during CAN module operation.
The user must ensure the maximum clock output frequency of the divider is 80 MHz or less.

Name:	CANCLKCON
Offset:	0xF9A


Bit	15	14	13	12	11	10	9	8
	CANCLKEN				CANCLKSEL[3:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	7	6	5	4	3	2	1	0
		CANCLKDIV[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 15 – CANCLKEN CAN Clock Generator Enable bit

Value	Description
`1`	CAN clock generation circuitry is enabled.
`0`	CAN clock generation circuitry is disabled.

Bits 11:8 – CANCLKSEL[3:0] CAN Clock Source Select bits⁽¹⁾

Value	Description
`0110-1111`	Reserved (no clock selected)
`0101`	F_VCO/4
`0100`	F_VCO/3
`0011`	F_VCO/2
`0010`	F_PLLO
`0001`	F_VCO
`0000`	0 (no clock selected)

Bits 6:0 – CANCLKDIV[6:0] CAN Clock Divider Select bits^(2,3)

Value	Description
`1111111`	Divide-by-128
. . .
`0000010`	Divide-by-3
`0000001`	Divide-by-2
`0000000`	Divide-by-1

DS70005633B

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