9.10.1 Oscillator Control Register
- Writes to this register require an unlock sequence.
- Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes.
- This bit should only be cleared in software.
Legend: y = Value set from Configuration bits on POR
| Name: | OSCCON(1) |
| Offset: | 0xF84 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COSC[2:0] | NOSC[2:0] | ||||||||
| Access | R | R | R | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | y | y | y | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKLOCK | LOCK | CF | OSWEN | ||||||
| Access | R/W | R | R | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 14:12 – COSC[2:0] Current Oscillator Selection bits (read-only)
| Value | Description |
|---|---|
111 |
Fast RC Oscillator (FRC) with Divide-by-n (FRCDIVN) |
110 |
Backup FRC (BFRC) |
101 |
Low-Power RC Oscillator (LPRC) |
100 |
Reserved – default to FRC |
011 |
Primary Oscillator (XT, HS, EC) with PLL (XTPLL, HSPLL, ECPLL) |
010 |
Primary Oscillator (XT, HS, EC) |
001 |
Fast RC Oscillator (FRC) with PLL (FRCPLL) |
000 |
Fast RC Oscillator (FRC) |
Bits 10:8 – NOSC[2:0] New Oscillator Selection bits(2)
| Value | Description |
|---|---|
111 |
Fast RC Oscillator (FRC) with Divide-by-n (FRCDIVN) |
110 |
Backup FRC (BFRC) |
101 |
Low-Power RC Oscillator (LPRC) |
100 |
Reserved – default to FRC |
011 |
Primary Oscillator (XT, HS, EC) with PLL (XTPLL, HSPLL, ECPLL) |
010 |
Primary Oscillator (XT, HS, EC) |
001 |
Fast RC Oscillator (FRC) with PLL (FRCPLL) |
000 |
Fast RC Oscillator (FRC) |
Bit 7 – CLKLOCK Clock Lock Enable bit
| Value | Description |
|---|---|
1 |
If (FCKSM0 = |
0 |
Clock and PLL selections are not locked; configurations may be modified. |
Bit 5 – LOCK PLL Lock Status bit (read-only)
| Value | Description |
|---|---|
1 |
Indicates that the PLL is in lock or the PLL start-up timer is satisfied. |
0 |
Indicates that the PLL is out of lock, the start-up timer is in progress, or the PLL is disabled. |
Bit 3 – CF Clock Fail Detect bit(3)
| Value | Description |
|---|---|
1 |
FSCM has detected a clock failure. |
0 |
FSCM has not detected a clock failure. |
Bit 0 – OSWEN Oscillator Switch Enable bit
| Value | Description |
|---|---|
1 |
Requests the oscillator switch to the selection specified by the NOSC[2:0] bits. |
0 |
Oscillator switch is complete. |