9.10.3 PLL Feedback Divider Register

Note:

The allowed range is 16-200 (decimal). The rest of the values are reserved and should be avoided. The power on the default feedback divider is 150 (decimal) with an 8 MHz FRC input clock. The VCO frequency is 1.2 GHz.

Legend: r = Reserved bit

Name:	PLLFBD
Offset:	0xF88


Bit	15	14	13	12	11	10	9	8
					Reserved[3:0]
Access					r	r	r	r
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PLLFBDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	1	0	1	1	0

Bits 11:8 – Reserved[3:0] Maintain as ‘`0`’

Bits 7:0 – PLLFBDIV[7:0] PLL Feedback Divider bits (also denoted as ‘M’, PLL multiplier)⁽¹⁾

Value	Description
11111111	Reserved
...
11001001	Reserved
11001000	Maximum (200 decimal)
...
10010110	150 (default)
...
00010000	Minimum (16 decimal)
00001111	Reserved
...
00000000	Reserved

DS70005633B

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