9.10.7 Reference Clock Control Low Register

Legend: HC = Hardware Clearable bit; HSC = Hardware Settable/Clearable bit

Name: REFOCONL
Offset: 0xFB8

Bit 15141312111098 
 ROEN ROSIDLROOUTROSLP ROSWENROACTIV 
Access R/WR/WR/WR/WR/W/HCR/HSC 
Reset 000000 
Bit 76543210 
     ROSEL[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 15 – ROEN Reference Clock Enable bit

ValueDescription
1

Reference oscillator is enabled on the REFCLKO pin.
0

Reference oscillator is disabled.

Bit 13 – ROSIDL Reference Clock Stop in Idle bit

ValueDescription
1 Reference oscillator continues to run in Idle mode.
0 Reference oscillator is disabled in Idle mode.

Bit 12 – ROOUT Reference Clock Output Enable bit

ValueDescription
1

Reference clock external output is enabled and available on the REFCLKO pin.
0

Reference clock external output is disabled.

Bit 11 – ROSLP Reference Clock Stop in Sleep bit

ValueDescription
1

Reference oscillator continues to run in Sleep modes.
0

Reference oscillator is disabled in Sleep modes.

Bit 9 – ROSWEN Reference Clock Output Enable bit

ValueDescription
1

Clock divider change (requested by changes to RODIVx) is requested or is in progress (set in software, cleared by hardware upon completion).
0

Clock divider change has been completed or is not pending.

Bit 8 – ROACTIV Reference Clock Status bit

ValueDescription
1

Reference clock is active; do not change the clock source.
0

Reference clock is stopped; the clock source and configuration may be safely changed.

Bits 3:0 – ROSEL[3:0] Reference Clock Source Select bits

ValueDescription
1111-1000 Reserved
0111 REFCLKI pin
0110 FVCO/4
0101 BFRC
0100 LPRC
0011 FRC
0010 Primary Oscillator
0001 Peripheral clock (FP)
0000 System clock (FOSC)