26.2.6.1 Dead-Time Delay for Brush DC Modes
Dead time is not required for the Brush DC modes, except during a direction mode change when the duty cycle is at or near 100%. It is expected that the user will switch between Forward mode and Reverse mode during run time. A direction change is accomplished by toggling the OUTM[0] bit in the application software when OUTM[2:0] = 101 or OUTM[2:0] = 100.
The direction change is synchronized to the CCP time-base period and occurs when sync_trig_in = 1.
When a direction change is made with the PWM Generator set for a low duty cycle, dead time is not required because the actively controlled switches will be turned off for a period of time before the direction change occurs. When the duty cycle is near 100%, dead time may be required to ensure that the top and bottom switches controlled by the module will be off for a minimum time.
When the module is in one of the Brush DC modes and the OUTM[0] is toggled in software to change direction, the following chain of events occurs:
- At the next PWM time-base Reset boundary, the two currently active pins (OCxA and OCxD or OCxB and OCxC) are driven to their Inactive states.
- If the value of the DT[5:0] bits is zero, then the new pair of output pins is made active immediately.
- If the value of the DT[5:0] bits is non-zero, then DT[5:0] is loaded into the dead-time delay counter when the MOD[0] bit is toggled. The new pair of output pins is made active after the dead-time counter expires.
Note that dead time is to be inserted only when the following occurs:
- The present value of OUTM[2:0] = 100 or 101,
AND
- OUTM[0] is toggled by user software.
When the above conditions are true, the dead time blanking will occur when sync_trig_in = 1. Figure 26-6 shows a timing diagram of a direction change when the dead time is programmed to a value of two cycles. Prior to the direction change, the OCxA pin receives the PWM Generator signal. The duty cycle is programmed to a value near 100%, and the output compare pulse terminates one CCP clock cycle prior to the end of the time-base period. The OCxD pin is driven active. At the PWM period Reset (sync_trig_in = 1), all four output pins are driven inactive for the duration of the dead-time count. After the dead-time delay, the OCxB pin is driven active and the OCxC pin receives the Output Compare signal.