26.2.8 Dead-Time Delay Generator

This section describes the dead-time delay generator that is available on the MCCP module. It is used in specific output modes of the module. The purpose of the dead-time delay generator is to:

  • Create two output signals, true and complement, from the single output signal of a PWM generator.
  • Provide a brief delay between the time when one signal is driven inactive and the other signal is driven active.

The dead-time delay generator contains edge detectors to monitor input signal transitions and a digital countdown timer. Each time an input signal edge occurs, the countdown timer is loaded with a programmable countdown value specified by the CCPx-CON3.DT[5:0] control bits. The rising edge of the inactive signal is delayed until the countdown timer counts to zero. If DT[5:0] = 0, the dead-time delay generator is effectively disabled and complementary output signals are produced with zero delay between the transitions on each output. A timing diagram for the dead-time delay generator are provided in Figure 26-11.

Note: When the time base operates from a clock source other than the system clock and TSYNC = 0, user software should not modify the DT[5:0] bits while ON = 1; unexpected results may occur.

There are special cases for dead-time generation:

  1. When the input signal pulse-width is equal to or less than the programmed dead-time value, the desired output results will not be obtained. Figure 26-12 depicts two scenarios where the duty cycle of the input signal is close to 0% and close to 100%. When the duty cycle is close to 0%, both outputs are driven inactive during the dead-time delay period. The out_high signal does not get driven active for any period of time. When the duty cycle is near 100%, both outputs are driven inactive for the dead-time period and the out_low signal does not get driven high for any period of time. These are regions of operation that should be avoided by the user.
  2. When the input duty cycle is set to 0%, there will be no transitions on the input signal. The out_high signal should remain LOW, and the out_low signal should remain HIGH.
  3. When the input duty cycle is set to 100%, there should be no transitions on the input signal. The out_high signal should remain HIGH, and the out_low signal should remain LOW.

As the input duty cycle approaches 0% or 100%, the dead-band delay time becomes a more significant portion of the input signal pulse-width. This effect causes a non-linear behavior between the requested duty cycle and the actual system response. Systems that are sensitive to this non linearity must avoid regions near 0% and 100% duty cycle, or use output feedback to compensate the duty cycle.