18.3.3 DAC Control Register


Bit	31	30	29	28	27	26	25	24
							TMCB[9:8]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	TMCB[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DACEN		IRQM[1:0]			UPDTMDIS		DACOEN
Access	R/W		R/W	R/W		R/W		R/W
Reset	0		0	0		0


Bit	7	6	5	4	3	2	1	0
					UPDTRG[1:0]		UPDATE	UPDREQ
Access					R/W	R/W	R	W
Reset					0	0	0	0

Bits 25:24 – TMCB[9:8] DACx Leading-Edge Blanking bits

These register bits specify the blanking period for the comparator, following changes to the DAC output during Change-of-State (COS), for the input signal selected by the HCFSEL[3:0] bits in SLPxCONL.

Bits 23:16 – TMCB[7:0] DACx Leading-Edge Blanking bits

These register bits specify the blanking period for the comparator, following changes to the DAC output during Change-of-State (COS), for the input signal selected by the HCFSEL[3:0] bits in SLPxCONL.

Bit 15 – DACEN Individual DACx Module Enable bit

Value	Description
1	Enables the DACx module.
0	Disables the DACx module to reduce power consumption; any pending Slope mode and/or underflow condition are cleared.

Bits 13:12 – IRQM[1:0] Interrupt Mode select bits

Value	Description
11	Generates an interrupt on either a rising or falling edge detect.
10	Generates an interrupt on a falling edge detect.
01	Generates an interrupt on a rising edge detect.
00	Interrupts are disabled.

Bit 10 – UPDTMDIS Update Transition Mode Disable bit

Value	Description
1	The Transition mode is disabled for DACDATA updates; the output voltage will be smoother, but the DAC may be slower in reaching the target voltage.
0	Transition mode is applied following DACDATA updates to reduce time to reach new specified DAC output voltage. DAC output voltage transient ripple may be introduced.

Bit 8 – DACOEN DACx Output Buffer Enable bit

Value	Description
1	DACx analog voltage is connected to the DACOUTx pin.
0	DACx analog voltage is not connected to the DACOUTx pin.

Bits 3:2 – UPDTRG[1:0] Update Trigger Select bits⁽¹⁾

Value	Description
`11`	Any write to DACDATxDACDAT[15:0]/DACLOW[15:0] or SLPDATxSLPDAT[15:0] sets the UPDATE bit immediately.
`10`	After any write(s) to DACDATxDACDAT[15:0]/DACLOW[15:0] or SLPDATxSLPDAT[15:0], a stop condition sets the UPDATE bit.
`01`	After any write(s) to DACDATxDACDAT[15:0]/DACLOW[15:0] or SLPDATxSLPDAT[15:0], a start condition sets the UPDATE bit
`00`	After any write(s) to DACDATxDACDAT[15:0]/DACLOW[15:0] or SLPDATxSLPDAT[15:0], the user must set DACCONx.UPDREQ bit manually.

Bit 1 – UPDATE DAC Register Update Status/Control bit

Value	Description
`1`	DAC register update is pending – user Data registers are not writable.
`0`	No DAC register update is pending.

Bit 0 – UPDREQ DAC Register Update Request bit

User software writes a ‘1’ to this bit location to request a DAC register update. The bit location always reads as ‘0’. The UPDATE status bit will indicate ‘1’ when an update is pending.

Name:	DACxCON
Offset:	0x1D48, 0x1D5C, 0x1D70, 0x1D84