18.3.6 DAC Slope x Control Register


Bit	31	30	29	28	27	26	25	24
	SLOPEN				HME	TWME	PSE
Access	R/W				R/W	R/W	R/W
Reset	0				0	0	0


Bit	23	22	21	20	19	18	17	16
								FFSEN
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	HCFSEL[3:0]				SLPSTOPA[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SLPSTOPB[3:0]				SLPSTRT[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – SLOPEN Slope Function Enable/On bit

Value	Description
1	Enables slope function.
0	Disables slope function; slope accumulator is disabled to reduce power consumption.

Bit 27 – HME Hysteretic Mode Enable bit

Value	Description
1	Enables Hysteretic mode for DACx.
0	Disables Hysteretic mode for DACx.

Bit 26 – TWME Triangle Wave Mode Enable bit

Value	Description
1	Enables Triangle Wave mode for DACx.
0	Disables Triangle Wave mode for DACx.

Bit 25 – PSE Positive Slope Mode Enable bit

Value	Description
1	Slope mode is positive (increasing).
0	Slope mode is negative (decreasing).

Bit 16 – FFSEN Fast First Step Mode Enable bit

Value	Description
1	Fast First Step mode is enabled.
0	Fast First Step mode is disabled.

Bits 15:12 – HCFSEL[3:0] Hysteretic Comparator Function Input Select bits

Refer to Table 18-6 for device-specific HCFSEL bit information.

Bits 11:8 – SLPSTOPA[3:0] Slope Stop A Signal Select bits

The selected Slope Stop A signal is logically OR’d with the selected Slope Stop B signal to terminate the slope function. Refer to Table 18-4 for device-specific SLPSTOPA bit information.

Bits 7:4 – SLPSTOPB[3:0] Slope Stop B Signal Select bits

The selected Slope Stop B signal is logically OR’d with the selected Slope Stop A signal to terminate the slope function. Refer to Table 18-5 for device-specific SLPSTOPB bit information.

Bits 3:0 – SLPSTRT[3:0] Slope Start Signal Select bits

Refer to Table 18-3 for device specific SLPSTRT bit information.

Name:	DACxSLPCON
Offset:	0x1D54, 0x1D68, 0x1D7C, 0x1D90, 0x1DA4, 0x1DB8, 0x1DCC, 0x1DE0