18.3.1 DAC Control 1 Register

Note: These bits should only be changed when DACON = 0 to avoid unpredictable behavior.
Name: DACCTRL1
Offset: 0x1D40

Bit 3130292827262524 
 RREN POSINLADJ[5:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000001 
Bit 2322212019181716 
  NEGINLADJ[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000001 
Bit 15141312111098 
 ON SIDLDNLADJ[4:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
      FCLKDIV[2:0] 
Access R/WR/WR/W 
Reset 000 

Bit 31 – RREN Ripple Reduction Enable bit

ValueDescription
1 Ripple Reduction mode is enabled.
0

Ripple Reduction mode is disabled.

Bits 29:24 – POSINLADJ[5:0] Positive INL Correction Value bits

The number of ones in this register controls the rise time of the PDM drivers. Reducing the number of ones in this register will increase the rise time. This value is shared by all of the PDM DACs.

Bits 22:16 – NEGINLADJ[6:0] Negative INL Correction Value bits

The number of ones in this register controls the fall time of the PDM drivers. Reducing the number of ones in this register will increase driver fall time. This bit field only exists if a type #2 filter is instantiated.

Bit 15 – ON Common DAC Module Enable bit

ValueDescription
1

Enables DAC modules.

0

Disables DAC modules and disables FSCM clocks to reduce power consumption; any pending Slope mode and/or underflow condition is cleared.

Bit 13 – SIDL DAC Stop in Idle Mode bit

ValueDescription
1

Discontinues module operation when device enters Idle mode.

0

Continues module operation in Idle mode.

Bits 12:8 – DNLADJ[4:0] DNL Adjustment Override bits

Each bit assert to a “1”overrides the DNL pulse stretcher finger control. Each “1” reduces the amount of DNL pulse stretching, thus reducing the amount of DNL correction. This value is shared by all of the PDM DACs

Bits 2:0 – FCLKDIV[2:0] Comparator Filter Clock Divider bits

ValueDescription
111

Divide-by-8

110

Divide-by-7

101

Divide-by-6

100

Divide-by-5

011

Divide-by-4

010

Divide-by-3

001

Divide-by-2

000

1x