18.3.1 DAC Control 1 Register
Note: These bits should only be changed when
DACON =
0 to avoid unpredictable behavior.| Name: | DACCTRL1 |
| Offset: | 0x1D40 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RREN | POSINLADJ[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NEGINLADJ[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | DNLADJ[4:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FCLKDIV[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 31 – RREN Ripple Reduction Enable bit
| Value | Description |
|---|---|
| 1 | Ripple Reduction mode is enabled. |
| 0 |
Ripple Reduction mode is disabled. |
Bits 29:24 – POSINLADJ[5:0] Positive INL Correction Value bits
Bits 22:16 – NEGINLADJ[6:0] Negative INL Correction Value bits
Bit 15 – ON Common DAC Module Enable bit
| Value | Description |
|---|---|
| 1 | Enables DAC modules. |
| 0 | Disables DAC modules and disables FSCM clocks to reduce power consumption; any pending Slope mode and/or underflow condition is cleared. |
Bit 13 – SIDL DAC Stop in Idle Mode bit
| Value | Description |
|---|---|
| 1 | Discontinues module operation when device enters Idle mode. |
| 0 | Continues module operation in Idle mode. |
Bits 12:8 – DNLADJ[4:0] DNL Adjustment Override bits
1” reduces the amount of
DNL pulse stretching, thus reducing the amount of DNL correction. This value is shared
by all of the PDM DACsBits 2:0 – FCLKDIV[2:0] Comparator Filter Clock Divider bits
| Value | Description |
|---|---|
| 111 | Divide-by-8 |
| 110 | Divide-by-7 |
| 101 | Divide-by-6 |
| 100 | Divide-by-5 |
| 011 | Divide-by-4 |
| 010 | Divide-by-3 |
| 001 | Divide-by-2 |
| 000 | 1x |
