13.3.7 DMA Channel x Interrupt Register
Legend: C = Clearable bit, HS = Hardware Settable bit
| Name: | DMAxSTAT |
| Offset: | 0x2318, 0x2344, 0x2370, 0x239C, 0x23C8, 0x23F4, 0x2420, 0x244C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAFLT3 | DMAFLT2 | ||||||||
| Access | R/C/HS | R/C/HS | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMAFLT[1:0] | DONE | HALF | OVERRUN | MATCH | DBUFWF | ||||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 9 – DMAFLT3 DMA Fault Status bit 3
| Value | Description |
|---|---|
| 1 | A bus read error has occurred; invalid data were received by the DMA. |
| 0 | No bus read error has occurred. |
Bit 8 – DMAFLT2 DMA Fault Status bit 2
| Value | Description |
|---|---|
| 1 | A bus read error has occurred; invalid data were received by the DMA. |
| 0 | No bus read error has occurred. |
Bits 7:6 – DMAFLT[1:0] DMA Fault Status bit 1 and bit 0
| Value | Description |
|---|---|
| 11 | Address Fault condition(s) |
| 10 | Access attempted to address higher than HADDR[23:0], not detected until actual access. |
| 01 | Access attempted to address lower than LADDR[23:0], but above the SFR range, not detected. |
| 00 | No DMA Fault condition |
Bit 5 – DONE DMA Complete Operation Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The DMA channel’s CNT[31:0] counter has reached 0. |
| 0 | The DMA channel’s CNT[31:0] counter has not reached 0. |
Bit 4 – HALF DMA 50% Watermark Level Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The DMA channel’s CNT[31:0] counter has reached the halfway point towards 0. |
| 0 | The DMA channel’s CNT[31:0] counter has not reached the halfway point towards 0. |
Bit 3 – OVERRUN DMA Channel Overrun Flag bit
| Value | Description |
|---|---|
| 1 | The DMA channel is triggered while it is still completing the operation based on the previous trigger. |
| 0 | The overrun condition has not occurred. |
Bit 1 – MATCH Pattern Match Status bit (see Pattern Match)
| Value | Description |
|---|---|
| 1 | Pattern match has been detected. |
| 0 | Pattern match has not been detected. |
Bit 0 – DBUFWF Buffered Data Write Flag bit
| Value | Description |
|---|---|
| 1 | The content of the DBUF[31:0] (DMABUF[31:0]) bits has not been stored into the location specified in DADDR[23:0] or SADDR[23:0] in Null Write mode. |
| 0 | The content of the DBUF[31:0] (DMABUF[31:0]) bits has been stored into the location specified in DADDR[23:0] or SADDR[23:0] in Null Write mode. |