13.3.13 DMA Channel x Invert Register

Name:	DMAxINV
Offset:	0x2330, 0x235C, 0x2388, 0x23B4, 0x23E0, 0x240C, 0x2438, 0x2464


Bit	31	30	29	28	27	26	25	24
	INV[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	INV[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	INV[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	INV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – INV[31:0] Inverter Register bits

When set high, the corresponding data bit(s) from the DMABUF register is (are) inverted (after set, then cleared, if applicable; see Priority and Bit Manipulation) before reaching the destination.