13.3.1 DMA Module Control Register
Legend: r = Reserved bit
| Name: | DMACON |
| Offset: | 0x2300 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRIORITY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 15 – ON DMA Module Enable bit
| Value | Description |
|---|---|
| 1 | Enables module. |
| 0 | Disables module. When set low, all state machines are reset, resulting in immediate termination of all active DMA operation(s); however, the contents of the control registers are NOT reset to their default settings. |
Bit 13 – SIDL DMA Stop in Idle bit
| Value | Description |
|---|---|
| 1 | When system enters Idle mode, the module stops operation. |
| 0 | When system enters Idle mode, the module continues operation. |
Bit 0 – PRIORITY Channel Priority Scheme Selection bit
| Value | Description |
|---|---|
| 1 | Round robin scheme |
| 0 | Fixed priority scheme |