13.3.3 DMA Low Address Limit Register

Note:

The LADDR[23:0] bits apply to data space only. SFR space outside the range from LADDR[23:0] to HADDR[23:0] is accessible by the DMA and will not result in an interrupt. Setting LADDR[23:0] to an address in SFR will, therefore, be ignored.

Name:	DMALOW
Offset:	0x2308


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	LADDR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	LADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:0 – LADDR[23:0] Low Limit Address bits⁽¹⁾

These bits indicate the lower address location below which the DMA module initiates a transaction, which results in the bus error trap, DMAFLT[1:0] = 01 and CHEN is cleared.

13.3.3 DMA Low Address Limit Register

Bits 23:0 – LADDR[23:0] Low Limit Address bits(1)

Bits 23:0 – LADDR[23:0] Low Limit Address bits⁽¹⁾