3.6.8.7.3 Instruction/Hazard Tracker

The Instruction/Hazard Tracker is a mechanism whereby hazard-related information is required while an instruction is progressing through the execute stages is captured in a FIFO for each issued instruction when that instruction is committed and enters the FPU pipeline X [0]-stage. The FIFO depth (default is four) defines how many instructions may be sequentially dispatched into the Execution stage before it is regarded as full.

Each FIFO entry includes the following information which is used during the X-stages.

  1. Entry valid flag
  2. Flags to indicate which Functional Block (function and operation precision) is targeted.
  3. Operand source register identification and valid flag such that RAW hazards may be identified as the instruction progresses.
  4. Flags to support Single Precision and Double Precision NaN propagation logic.
  5. Flag to indicate if an instruction is FDIV or FSUB (where the operand order is reversed).
  6. Flag to indicate if an instruction is FMAC (special case for NaN propagation).
Each FIFO entry requires a ‘valid’ bit which is clear whenever the entry is empty or after it has been used in the WB-stage. This bit will inhibit any associated hazard detection after an instruction has retired.

Operation precision partially identifies the selected functional block but also directs the hazard logic. Single Precision operations need to only check for hazards involving single F-regs whereas Double Precision must check F-reg pairs for hazards.

Operand register identification and valid flags log which F-regs are used for operands (not all instructions require all three source operands) for hazard tracking. In addition, each FIFO entry includes the following information (also detected in the RD-stage) which is used during the instruction WB-stage.

  1. Flags to indicate if any result is to be written to an F-reg and whether the FSR is to be updated.
  2. Result destination register (and context) identification (defined as DP targets). Additional flags select the active registers (i.e., DP F-reg pair or one of two SP F-reg destinations).
  3. Flag to indicate if the instruction permits a FTZ override of the result.
  4. CPU A-stage instruction address to capture in the FEAR (if enabled) should the instruction generate an exception.
  5. Flags to indicate if the instruction is a FAND or IOR, and the associated FSR/FCR/FEAR target register select bits.
  6. The presence of a subnormal operand (when SAZ mode is disabled) is captured and used to signal the subnormal exception (i.e., at the same time as any other exceptions the instruction may generate).