15.4.3.11.1 Capture to Trigger

To support LLC Operating mode, a capture to trigger is available. When triggered, hardware will capture the time base value, perform a computation and store the result in one of the PGxTRIGy registers. The feature is enabled with the CAPTREN (PGxIOCON1[19]) bit and the CAPTRSEL[1:0] (PGxIOCON1[17:16]) bits define the PGxTRIGy (where y = C, D, E or F) register to store the result. The feature works in conjunction with the time base capture and stores the time base in the PGxCAP register as defined by its control bits.

The trigger value to be stored in the Trigger register is 50% of the high time value, defined as:

Trigger Value = (PGxCAP - DTH)/2

Further mathematics can be performed on the trigger data using the offset and postscaler features of CAPTROFS[4:0] and CAPTRPS[4:0] in the PGxEVT2 register. The value stored in the PGxTRIGy resgister is:

PGxTRIGy = (Trigger value +CAPTROFS) / CAPTRPS

The CAPTR status bit in PGxSTAT[13] indicates that a new trigger value has been successfully stored in the selected Trigger register. It is cleared when PGxCAP is read or CAPTRSEL[1:0] is written.

Table 15-12 summarizes the operation of the capture features.

Table 15-12. Capture Operation Summary

LLC Mode

(MOD[2:0] = 011)

CAPENCAPTRENCapture Operation
No00
  • Continues per CAPSRC[2:0] after PGxCAP read OR.
  • Continues immediately after PGxCAP read AND setting PGxCAP[0] high.
01
  • Same as immediately above PLUS
  • Stores trigger value per CAPTRSEL[1:0] with offset based on CAPTROFS[4:0].
10
  • Continues per CAPSRC[2:0] (no PGxCAP read needed).
11
  • Same as immediately above PLUS
  • Stores trigger value per CAPTRSEL[1:0] with offset based on CAPTROFS[4:0].
Yesx0
  • Continues per CAPSRC[2:0] in cycle 1 when STEER = 0.
1
  • Same as immediately above PLUS
  • Stores trigger value per CAPTRSEL[1:0] with offset based on CAPTROFS[4:0].
Note: Trigger value is equal to exactly one half of the high time count value in LLC mode.