20.3.2 UARTx Status Register
- The receive watermark interrupt is not set if PERIF, FERIF or TXCIF is set and the corresponding IE bit is set.
Legend: S = Settable bit, HS = Hardware Settable bit
| Name: | UxSTAT |
| Offset: | 0x1704, 0x1744, 0x1784 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TXWM[2:0] | RXWM[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXWRE | STPMD | TXBE | TXBF | RCIDL | XON | RXBE | RXBF | ||
| Access | R/W/HS | R/W | R/S | R | R | R | R/S | R | |
| Reset | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXMTIE | PERIE | ABDOVIE | CERIE | FERIE | RXBKIE | RXFOIE | TXCIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXMTIF | PERIF | ABDOVIF | CERIF | FERIF | RXBKIF | RXFOIF | TXCIF | ||
| Access | R | R | R/W/HS | R/W/HC | R | R/W/HC | R/W/HC | R/W/HC | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 30:28 – TXWM[2:0] UART Transmit Interrupt Select bits
| Value | Description |
|---|---|
111 |
Sets transmit interrupt when there is one empty slot left in the buffer. |
| . . . | |
010 |
Sets transmit interrupt when there are six empty slots or more in the buffer. |
001 |
Sets transmit interrupt when there are seven empty slots or more in the buffer. |
000 |
Sets transmit interrupt when there are eight empty slots in the buffer; TX buffer is empty. |
Bits 26:24 – RXWM[2:0] UART Receive Interrupt Select bits(1)
| Value | Description |
|---|---|
111 |
Triggers receive interrupt when there are eight words in the buffer; RX buffer is full. |
| . . . | |
001 |
Triggers receive interrupt when there are two words or more in the buffer. |
000 |
Triggers receive interrupt when there is one word or more in the buffer. |
Bit 23 – TXWRE TX Write Transmit Error Status bit
LIN and Parity Modes:
1 = A new byte was written when buffer was full or when P2[8:0] =
0 (must be cleared by software).
0 = No error
Address Detect Mode:
1 = A new byte was written when buffer was full or to P1[8:0] when
P1x was full (must be cleared by software).
0 = No error
Other Modes:
1 = A new byte was written when buffer was full (must be cleared by
software).
0 = No error
Bit 22 – STPMD Stop Bit Detection Mode bit
| Value | Description |
|---|---|
1 |
Triggers RXIF at the end of the last Stop bit. |
0 |
Triggers RXIF in the middle of the first (or second, depending on the STP[1:0] setting) Stop bit. |
Bit 21 – TXBE UART TX Buffer Empty Status bit
| Value | Description |
|---|---|
1 |
Transmit
buffer is empty; writing ‘1’ when TXEN = 0 will
reset the TX FIFO pointers and counters. |
0 |
Transmit buffer is not empty. |
Bit 20 – TXBF UART TX Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Transmit buffer is full. |
0 |
Transmit buffer is not full. |
Bit 19 – RCIDL Receive Idle bit
| Value | Description |
|---|---|
1 |
UART RX line is in the Idle state. |
0 |
UART RX line is receiving something. |
Bit 18 – XON UART in XON Mode bit
Only valid when FLO[1:0] control bits are set to XON/XOFF mode.
| Value | Description |
|---|---|
1 |
UART has received XON. |
0 |
UART has not received XON, or XOFF was received. |
Bit 17 – RXBE UART RX Buffer Empty Status bit
| Value | Description |
|---|---|
1 |
Receive buffer is empty; writing ‘ |
0 |
Receive buffer is not empty. |
Bit 16 – RXBF UART RX Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Receive buffer is full. |
0 |
Receive buffer is not full. |
Bit 15 – TXMTIE Transmit Shifter Empty Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 14 – PERIE Parity Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 13 – ABDOVIE Auto-Baud Rate Acquisition Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 12 – CERIE Checksum Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 11 – FERIE Framing Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 10 – RXBKIE Receive Break Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 9 – RXFOIE Receive Buffer Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 8 – TXCIE Transmit Collision Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled. |
0 |
Interrupt is disabled. |
Bit 7 – TXMTIF Transmit Shifter Empty Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Transmit Shift Register (TSR) is empty (TXMTIF bit gets set at the end of the last Stop bit; TXMTIF bit behavior is independent of the STPMD bit). |
0 |
Transmit Shift Register is not empty. |
Bit 6 – PERIF Parity Error/Address Received
LIN and Parity Modes:
1 = Parity error detected
0 = No parity error detected
Address Mode:
1 = Address received
0 = No address detected
All Other Modes:
Not used.
Bit 5 – ABDOVIF Auto-Baud Rate Acquisition Interrupt Flag bit
| Value | Description |
|---|---|
1 |
BRG rolled over during the auto-baud rate acquisition sequence. |
0 |
BRG has not rolled over during the auto-baud rate acquisition sequence. |
Bit 4 – CERIF Checksum Error Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Checksum error |
0 |
No checksum error |
Bit 3 – FERIF Framing Error Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Framing Error: Inverted level of the Stop bit corresponding to the topmost character in the buffer; propagates through the buffer with the received character. |
0 |
No framing error |
Bit 2 – RXBKIF Receive Break Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
A break was received. |
0 |
No break was detected. |
Bit 1 – RXFOIF Receive Buffer Overflow Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Receive buffer has overflowed. |
0 |
Receive buffer has not overflowed. |
Bit 0 – TXCIF Transmit Collision Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Transmitted word is not equal to the received word. |
0 |
Transmitted word is equal to the received word. |