20.3.1 UARTx Configuration Register
| Name: | UxCON |
| Offset: | 0x1700, 0x1740, 0x1780 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SLPEN | ACTIVE | CLKMOD | CLKSEL[1:0] | HALFDPLX | |||||
| Access | R/W | R | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RUNOVF | RXPOL | STP[1:0] | C0EN | TXPOL | FLO[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | WUE | RXBIMD | BRKOVR | SENDB | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W/HC | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BRGS | ABDEN | TXEN | RXEN | MODE[3:0] | |||||
| Access | R/W | R/W/HC | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – SLPEN Run During Sleep Enable bit
| Value | Description |
|---|---|
1 |
UART BRG clock runs during Sleep. |
0 |
UART BRG clock is turned off during Sleep. |
Bit 30 – ACTIVE UART Running Status bit
| Value | Description |
|---|---|
1 |
UART clock request is active (user should not update the UxCON register). |
0 |
UART clock request is not active (user can update the UxCON register). |
Bit 27 – CLKMOD Baud Clock Generation Mode Select bit
| Value | Description |
|---|---|
1 |
Uses fractional Baud Rate Generation. |
0 |
Uses legacy divide-by-x counter for baud clock generation (x = 4 or 16 depending on the BRGS bit). |
Bits 26:25 – CLKSEL[1:0] Baud Clock Source Selection bits
Bit 24 – HALFDPLX UART Half-Duplex Selection Mode bit
| Value | Description |
|---|---|
1 |
Half-Duplex mode |
0 |
Full-Duplex mode |
Bit 23 – RUNOVF Run During Overflow Condition Mode bit
| Value | Description |
|---|---|
1 |
When an Overflow Error (RXFOIF) condition is detected, the RX shifter continues to run so as to remain synchronized with incoming RX data; data are not transferred to UxRXB when it is full (i.e., no UxRXB data are overwritten). |
0 |
When an Overflow Error (RXFOIF) condition is detected, the RX shifter stops accepting new data; data are transferred to UxRXB when one empty slot becomes available in the buffer (Legacy mode). |
Bit 22 – RXPOL UART Receive Polarity bit
| Value | Description |
|---|---|
1 |
Inverts RX polarity; Idle state is low. |
0 |
Input is not inverted; Idle state is high. |
Bits 21:20 – STP[1:0] Number of Stop Bits Selection bits
| Value | Description |
|---|---|
11 |
Two Stop bits sent, one checked at receive. |
10 |
Two Stop bits sent, two checked at receive. |
01 |
1.5 Stop bits sent, 1.5 checked at receive. |
00 |
One Stop bit sent, one checked at receive. |
Bit 19 – C0EN Enable Legacy Checksum (C0) Transmit and Receive bit
| Value | Description |
|---|---|
1 |
Checksum mode 1 (enhanced LIN checksum in LIN mode; add all TX/RX words in all other modes). |
0 |
Checksum mode 0 (legacy LIN checksum in LIN mode; not used in all other modes). |
Bit 18 – TXPOL UART Transmit Polarity bit
| Value | Description |
|---|---|
1 |
Inverts TX polarity; TX is low in Idle state. |
0 |
Output data are not inverted; TX output is high in Idle state. |
Bits 17:16 – FLO[1:0] Flow Control Enable
bits (only valid when MODE[3:0] =
0xxx)
| Value | Description |
|---|---|
11 |
Reserved |
10 |
UxRTS-UxDSR (for TX side)/UxCTS-UxDTR (for RX side) hardware flow control |
01 |
XON/XOFF software flow control |
00 |
Flow control off |
Bit 15 – ON UART Enable bit
| Value | Description |
|---|---|
1 |
UART is ready to transmit and receive. |
0 |
UART state machine, FIFO buffer pointers and counters are reset; registers are readable and writable. |
Bit 13 – SIDL UART Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when device enters Idle mode. |
0 |
Continues module operation in Idle mode. |
Bit 12 – WUE Wake-up Enable bit
| Value | Description |
|---|---|
1 |
Module will continue to sample the UxRX pin – interrupt generated on falling edge, bit cleared in hardware on following rising edge; if ABDEN is set, Auto-Baud Detection (ABD) will begin immediately. |
0 |
UxRX pin is not monitored nor rising edge detected. |
Bit 11 – RXBIMD Receive Break Interrupt Mode bit
| Value | Description |
|---|---|
1 |
RXBKIF flag when a minimum of 23 (DMX)/11 (asynchronous or LIN/J2602) low bit periods are detected. |
0 |
RXBKIF flag when the Break makes a low-to-high transition after being low for at least 23/11 bit periods. |
Bit 9 – BRKOVR Send Break Software Override bit
Overrides the TX Data Line:
| Value | Description |
|---|---|
1 |
Makes the TX
line active (Output 0 when TXPOL = 0, Output 1 when TXPOL =
1). |
0 |
TX line is driven by the shifter. |
Bit 8 – SENDB UART Transmit Break bit(1)
| Value | Description |
|---|---|
1 |
Sends Sync Break on next transmission; cleared by hardware upon completion. |
0 |
Sync Break transmission is disabled or has completed. |
Bit 7 – BRGS High Baud Rate Select bit
| Value | Description |
|---|---|
1 |
High speed |
0 |
Low speed |
Bit 6 – ABDEN Auto-Baud Detect
Enable bit (read-only when MODE[3:0] =
1xxx)
| Value | Description |
|---|---|
1 |
Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion. |
0 |
Baud rate measurement is disabled or has completed. |
Bit 5 – TXEN UART Transmit Enable bit
| Value | Description |
|---|---|
1 |
Transmit enabled – except during Auto-Baud Detection. |
0 |
Transmit disabled – all transmit counters, pointers and state machines are reset; TX buffer is not flushed, status bits are not reset. |
Bit 4 – RXEN UART Receive Enable bit
| Value | Description |
|---|---|
1 |
Receive enabled – except during Auto-Baud Detection. |
0 |
Receive disabled – all receive counters, pointers and state machines are reset; RX buffer is not flushed, status bits are not reset. |
Bits 3:0 – MODE[3:0] UART Mode bits
| Value | Description |
|---|---|
| Other |
Reserved |
1111 |
Smart card |
1110 |
IrDA® |
1101 |
Reserved |
1100 |
LIN Commander/Responder |
1011 |
LIN Responder only |
1010 |
DMX |
1001-0101 |
Reserved |
0100 |
Asynchronous 9-bit UART with address detect, ninth bit = |
0011 |
Asynchronous 8-bit UART without address detect, ninth bit is used as an even parity bit. |
0010 |
Asynchronous 8-bit UART without address detect, ninth bit is used as an odd parity bit. |
0001 |
Asynchronous 7-bit UART |
0000 |
Asynchronous 8-bit UART |