15.4.3.10.1 Synchronizing Multiple PWM Generator Buffer Updates
The MSTEN control bit (PGxCON[27]) allows the PWM Generator to
control register updates in other PWM Generators. The UPDREQ control and UPDATE status bits
can be effectively broadcast to other PWM Generators to allow coherent register updates
among a set of PWM Generators that control a common function. When MSTEN is set and the
user software (or the PWM Generator hardware) sets the UPDREQ control bit, this event will
be broadcast to all other PWM Generators. If UPDMOD[2:0] = 01x in a PWM Generator that receives the request, the receiving module will
set its local UPDREQ bit. The local UPDATE status bit will then be cleared when the local
registers have been updated. The user software may set a local UPDREQ bit manually.
| UPDMOD[2:0] | Mode | Description |
|---|---|---|
000 | SOC | Update Data registers at the start of
next PWM cycle if UPDREQ = 1. The UPDATE status bit will be
cleared automatically after the update occurs. |
001 | Immediate | Update Data registers immediately, or
as soon as possible, if UPDREQ = 1. The UPDATE status bit
will be cleared automatically after the update occurs. |
010 | Client SOC | Update Data registers at the start of
next cycle if a host update request is received. A host update request will be
transmitted if MSTEN = 1 and UPDREQ = 1 for
the requesting PWM Generator. |
011 | Client Immediate | Update Data registers immediately, or
as soon as possible, when a host update request is received. A host update
request will be transmitted if MSTEN = 1 and UPDREQ =
1 for the requesting PWM Generator. |
- The UPDREQ bit must be set at least three sys_clk cycles, followed by three PGx_clk cycles, followed by another three sys_clk cycles, before the next PWM cycle boundary in order to take effect. Otherwise, the data update will be delayed until the following PWM cycle.
Synchronizing Multiple PWM Generator data updates:
- Configure host PG for SOC updates and write MSTEN = '1'.
- Configure client(s) PG for 'Client SOC' mode by writing UPDMOD = 0b0101.
- Configure host PWM interrupt for SOC (default).
- When interrupt event occurs:
- Read host UPDATE bit and verify it is '0'.
- Write new data values to all PWM generators (PGx).
- Set host UPDREQ bit to a '1' to commit data to PWM buffer.
On the next SOC, all PWM generators configured as clients will operate with new data values.
For the purpose of Data register updates, a PWM cycle length is variable. A PWM cycle may comprise one, two or four timer cycles, depending on the PWM Operating mode and the Output mode that is selected. The PWM Data registers may be updated on the next, second or fourth timer cycle when a SOC update has been requested. Table 15-11 summarizes the number of timer cycles between each SOC update vs. the PWM Generator Operating mode and the Output mode.
| PWM Mode | Output Mode | Timer Cycles per PWM Cycle | Timer Cycles per Interrupt and Data Register Update |
|---|---|---|---|
| Independent Edge, Dual PWM or Variable Phase | Independent Output, Complementary | 1 | 1 |
| Independent Edge, Dual PWM or Variable Phase | Push-Pull | 2 | 2 |
| Center-Aligned | Independent Output, Complementary | 2 | 2 |
| Center-Aligned | Push-Pull | 4 | 4 |
| Double Update Center-Aligned or Dual Edge Center-Aligned | Independent Output, Complementary | 2 | 1 |
| Double Update Center-Aligned or Dual Edge Center-Aligned | Push-Pull | 4 | 1 |