14.9.5 XDMAC Global Interrupt Disable Register
| Name: | XDMAC_GID |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ID31 | ID30 | ID29 | ID28 | ID27 | ID26 | ID25 | ID24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ID23 | ID22 | ID21 | ID20 | ID19 | ID18 | ID17 | ID16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – IDx XDMAC Channel x Interrupt Disable
| Value | Description |
|---|---|
| 0 | This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified. |
| 1 | The corresponding mask bit is reset. The Channel x Interrupt Status register interrupt (XDMAC_GIS) is masked. |