14.9.5 XDMAC Global Interrupt Disable Register

Name: XDMAC_GID
Offset: 0x10
Reset: 
Property: Write-only

Bit 3130292827262524 
 ID31ID30ID29ID28ID27ID26ID25ID24 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 ID23ID22ID21ID20ID19ID18ID17ID16 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 ID15ID14ID13ID12ID11ID10ID9ID8 
Access WWWWWWWW 
Reset  
Bit 76543210 
 ID7ID6ID5ID4ID3ID2ID1ID0 
Access WWWWWWWW 
Reset  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – IDx XDMAC Channel x Interrupt Disable

ValueDescription
0

This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified.

1

The corresponding mask bit is reset. The Channel x Interrupt Status register interrupt (XDMAC_GIS) is masked.