14.9.6 XDMAC Global Interrupt Mask Register
| Name: | XDMAC_GIM |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IM31 | IM30 | IM29 | IM28 | IM27 | IM26 | IM25 | IM24 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IM23 | IM22 | IM21 | IM20 | IM19 | IM18 | IM17 | IM16 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IM15 | IM14 | IM13 | IM12 | IM11 | IM10 | IM9 | IM8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IM7 | IM6 | IM5 | IM4 | IM3 | IM2 | IM1 | IM0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – IMx XDMAC Channel x Interrupt Mask
| Value | Description |
|---|---|
| 0 | This bit indicates that the channel x interrupt source is masked. The interrupt line is not raised. |
| 1 | This bit indicates that the channel x interrupt source is unmasked. |