14.9.24 XDMAC Channel x Interrupt Mask Register [x = 0..31]
| Name: | XDMAC_CIM |
| Offset: | 0x68 + n*0x40 [n=0..31] |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCIM | ROIM | WBEIM | RBEIM | FIM | DIM | LIM | BIM | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – TCIM Transfer Count Overflow Error Interrupt Mask
| Value | Description |
|---|---|
| 0 |
Transfer count overflow interrupt is masked. |
| 1 |
Transfer count overflow interrupt is activated. |
Bit 6 – ROIM Request Overflow Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Request overflow interrupt is masked. |
| 1 | Request overflow interrupt is activated. |
Bit 5 – WBEIM Write Bus Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Bus error interrupt is masked. |
| 1 | Bus error interrupt is activated. |
Bit 4 – RBEIM Read Bus Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | Bus error interrupt is masked. |
| 1 | Bus error interrupt is activated. |
Bit 3 – FIM End of Flush Interrupt Mask
| Value | Description |
|---|---|
| 0 | End of flush interrupt is masked. |
| 1 | End of flush interrupt is activated. |
Bit 2 – DIM End of Disable Interrupt Mask
| Value | Description |
|---|---|
| 0 | End of disable interrupt is masked. |
| 1 | End of disable interrupt is activated. |
Bit 1 – LIM End of Linked List Interrupt Mask
| Value | Description |
|---|---|
| 0 | End of linked list interrupt is masked. |
| 1 | End of linked list interrupt is activated. |
Bit 0 – BIM End of Block Interrupt Mask
| Value | Description |
|---|---|
| 0 | Block interrupt is masked. |
| 1 | Block interrupt is activated. |