14.9.1 XDMAC Global Type Register
Reset: The register reset values depend on the instance of the XDMAC:
Instance | Reset Value |
---|---|
XDMAC0, XDMAC1 | 0x004A201F |
XDMAC2 | 0x00002007 |
Name: | XDMAC_GTYPE |
Offset: | 0x00 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
NB_REQ[6:0] | |||||||||
Access | R | R | R | R | R | R | R | ||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FIFO_SZ[10:3] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FIFO_SZ[2:0] | NB_CH[4:0] | ||||||||
Access | R | R | R | R | R | R | R | R | |
Reset |
Bits 22:16 – NB_REQ[6:0] Number of Peripheral Requests Minus One
Bits 15:5 – FIFO_SZ[10:0] Number of Bytes
The FIFO size is given by the formula: Number of bytes + 8.