14.9.14 XDMAC Global Channel Read Write Resume Register
| Name: | XDMAC_GRWR |
| Offset: | 0x44 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RWR31 | RWR30 | RWR29 | RWR28 | RWR27 | RWR26 | RWR25 | RWR24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RWR23 | RWR22 | RWR21 | RWR20 | RWR19 | RWR18 | RWR17 | RWR16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RWR15 | RWR14 | RWR13 | RWR12 | RWR11 | RWR10 | RWR9 | RWR8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RWR7 | RWR6 | RWR5 | RWR4 | RWR3 | RWR2 | RWR1 | RWR0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – RWRx XDMAC Channel x Read Write Resume
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
Read and write requests are serviced. |