14.9.14 XDMAC Global Channel Read Write Resume Register

Name: XDMAC_GRWR
Offset: 0x44
Reset: 
Property: Write-only

Bit 3130292827262524 
 RWR31RWR30RWR29RWR28RWR27RWR26RWR25RWR24 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 RWR23RWR22RWR21RWR20RWR19RWR18RWR17RWR16 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 RWR15RWR14RWR13RWR12RWR11RWR10RWR9RWR8 
Access WWWWWWWW 
Reset  
Bit 76543210 
 RWR7RWR6RWR5RWR4RWR3RWR2RWR1RWR0 
Access WWWWWWWW 
Reset  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – RWRx XDMAC Channel x Read Write Resume

ValueDescription
0

No effect.

1

Read and write requests are serviced.