14.9.22 XDMAC Channel x Interrupt Enable Register [x=0..31]

Name: XDMAC_CIE
Offset: 0x60 + n*0x40 [n=0..31]
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 TCIEROIEWBIERBIEFIEDIELIEBIE 
Access WWWWWWWW 
Reset  

Bit 7 – TCIE Transfer Count Overflow Error Interrupt Enable

ValueDescription
0

No effect.

1

Enables transfer count overflow error interrupt.

Bit 6 – ROIE Request Overflow Error Interrupt Enable

ValueDescription
0

No effect.

1

Enables request overflow error interrupt.

Bit 5 – WBIE Write Bus Error Interrupt Enable

ValueDescription
0

No effect.

1

Enables write bus error interrupt.

Bit 4 – RBIE Read Bus Error Interrupt Enable

ValueDescription
0

No effect.

1

Enables read bus error interrupt.

Bit 3 – FIE End of Flush Interrupt Enable

ValueDescription
0

No effect.

1

Enables end of flush interrupt.

Bit 2 – DIE End of Disable Interrupt Enable

ValueDescription
0

No effect.

1

Enables end of disable interrupt.

Bit 1 – LIE End of Linked List Interrupt Enable

ValueDescription
0

No effect.

1

Enables end of linked list interrupt.

Bit 0 – BIE End of Block Interrupt Enable

ValueDescription
0

No effect.

1

Enables end of block interrupt.