14.9.3 XDMAC Global Weighted Arbiter Configuration Register
Note:
- PW0/1: when a memory-to-peripheral transaction occurs, the peripheral write transaction may be asserted at the same time as a memory write transaction. The write port arbiter grants bus access to the highest transaction weight first, then the internal weight counter is decremented. When the internal weight counter reaches 0, it is reloaded with PWx. If PW0=0 and PW1 = 0, the arbitration method is round-robin.
- PW2/3: When a peripheral-to-memory transaction occurs, the peripheral read transaction may be asserted at the same time as a memory read transaction. The Read Port Arbiter grants bus access to the highest transaction weight first, then the internal weight counter is decremented. When the internal weight counter reaches 0, it is reloaded with PWx. If PW2=0 and PW3 = 0, the arbitration method is round-robin.
| Name: | XDMAC_GWAC |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PW3[3:0] | PW2[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PW1[3:0] | PW0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:12 – PW3[3:0] Pool Weight 3
Memory transaction weight for read port arbiter. This is exactly the peripheral read transaction weight of a memory-tomemory transfer.
Bits 11:8 – PW2[3:0] Pool Weight 2
Peripheral transaction weight for read port arbiter. This is exactly the peripheral read transaction weight of a peripheral-tomemory transfer.
Bits 7:4 – PW1[3:0] Pool Weight 1
Memory transaction weight for write port arbiter. This is exactly the memory write transaction weight of a memory-to-memory transfer.
Bits 3:0 – PW0[3:0] Pool Weight 0
Peripheral transaction weight for write port arbiter. This is exactly the peripheral write transaction weight of a memory-to-peripheral transfer.