14.9.16 XDMAC Global Channel Write Suspend Status Register
Name: | XDMAC_GWSS |
Offset: | 0x2C |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
WSS31 | WSS30 | WSS29 | WSS28 | WSS27 | WSS26 | WSS25 | WSS24 | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
WSS23 | WSS22 | WSS21 | WSS20 | WSS19 | WSS18 | WSS17 | WSS16 | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
WSS15 | WSS14 | WSS13 | WSS12 | WSS11 | WSS10 | WSS9 | WSS8 | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WSS7 | WSS6 | WSS5 | WSS4 | WSS3 | WSS2 | WSS1 | WSS0 | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – WSS XDMAC Channel x Write Suspend Status
Value | Description |
---|---|
0 |
The write channel is not suspended. |
1 |
The source requests for channel x are no longer serviced by the system scheduler. |