14.9.11 XDMAC Global Channel Read Suspend Register
| Name: | XDMAC_GRS |
| Offset: | 0x30 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RS31 | RS30 | RS29 | RS28 | RS27 | RS26 | RS25 | RS24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RS23 | RS22 | RS21 | RS20 | RS19 | RS18 | RS17 | RS16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RS15 | RS14 | RS13 | RS12 | RS11 | RS10 | RS9 | RS8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RS7 | RS6 | RS5 | RS4 | RS3 | RS2 | RS1 | RS0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – RSx XDMAC Channel x Read Suspend
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 |
The source requests for channel n are no longer serviced by the system scheduler. |