14.9.21 XDMAC Global Channel Software Flush Request Register

Name: XDMAC_GSWF
Offset: 0x50
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 SWF31SWF30SWF29SWF28SWF27SWF26SWF25SWF24 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 SWF23SWF22SWF21SWF20SWF19SWF18SWF17SWF16 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SWF15SWF14SWF13SWF12SWF11SWF10SWF9SWF8 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 SWF7SWF6SWF5SWF4SWF3SWF2SWF1SWF0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – SWFx XDMAC Channel x Software Flush Request

ValueDescription
0

No effect.

1

Requests a DMA transfer flush for channel x. This bit is only relevant when the transfer is source peripheral synchronized.