14.9.2 XDMAC Global Configuration Register
- WRxP fields: to maximize system performance and avoid system head of line blocking, verify that (WRHP+1)+(WRMP+1)+(WRLP+1) is less than or equal to the system buffering capability (i.e., the size of addresses and write data buffer in the system bus interconnect).
- RDSG/RDxP fields: to maximize system performance and avoid system head of line blocking, verify that (RDSG+1)(RDHP+1)(RDMP+1)+(RDLP+1) is less than or equal to the system read buffering capability (i.e., the size of addresses buffer in the system bus interconnect).
- WRxP, RDSG, RDxP fields are related to the RAQ and WAQ DDR queues, defined respectively in “Read Address Channel” and “Write Address Channel” in the section “Universal DDR Memory Controller (UDDRC)”.
| Name: | XDMAC_GCFG |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RDSG[3:0] | RDLP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RDMP[3:0] | RDHP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WRLP[3:0] | WRMP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WRHP[3:0] | CGDISIF | CGDISFIFO | CGDISPIPE | CGDISREG | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:28 – RDSG[3:0] Read Queue Scatter Gather Outstanding Limit
RDSG+1 is the maximum number of active transactions for descriptor read access.
Bits 27:24 – RDLP[3:0] Read Queue Low Priority Outstanding Limit
RDLP+1 is the maximum number of active transactions for read access (memory) of a memory-to-memory transfer.
Bits 23:20 – RDMP[3:0] Read Queue Medium Priority Outstanding Limit
RDMP+1 is the maximum number of active transactions for read access (memory) of a memory-to-peripheral transfer.
Bits 19:16 – RDHP[3:0] Read Queue High Priority Outstanding Limit
RDHP+1 is the maximum number of active transactions for read access (peripheral) of a peripheral-to-memory transfer.
Bits 15:12 – WRLP[3:0] Write Queue Low Priority Outstanding Limit
WRLP+1 is the maximum number of active transactions for write access (memory) of a memory-to-memory transfer.
Bits 11:8 – WRMP[3:0] Write Queue Medium Priority Outstanding Limit
WRMP+1 is the maximum number of active transactions for write access (memory) of peripheral-to-memory transfer.
Bits 7:4 – WRHP[3:0] Write Queue High Priority Outstanding Limit
WRHP+1 is the maximum number of active transactions for write access (peripheral) of a memory-to-peripheral transfer.
Bit 3 – CGDISIF Bus Interface Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the system bus interface. |
| 1 | The automatic clock gating is disabled for the system bus interface. |
Bit 2 – CGDISFIFO FIFO Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the main FIFO. |
| 1 | The automatic clock gating is disabled for the main FIFO. |
Bit 1 – CGDISPIPE Pipeline Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the main pipeline. |
| 1 | The automatic clock gating is disabled for the main pipeline. |
Bit 0 – CGDISREG Configuration Registers Clock Gating Disable
| Value | Description |
|---|---|
| 0 | The automatic clock gating is enabled for the configuration registers. |
| 1 | The automatic clock gating is disabled for the configuration registers. |