14.9.12 XDMAC Global Channel Write Suspend Register
| Name: | XDMAC_GWS |
| Offset: | 0x38 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WS31 | WS30 | WS29 | WS28 | WS27 | WS26 | WS25 | WS24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WS23 | WS22 | WS21 | WS20 | WS19 | WS18 | WS17 | WS16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WS15 | WS14 | WS13 | WS12 | WS11 | WS10 | WS9 | WS8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WS7 | WS6 | WS5 | WS4 | WS3 | WS2 | WS1 | WS0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – WSx XDMAC Channel x Write Suspend
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 |
Destination requests are no longer routed to the scheduler. |