14.9.17 XDMAC Global Channel Read Resume Register
| Name: | XDMAC_GRR |
| Offset: | 0x34 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RR31 | RR30 | RR29 | RR28 | RR27 | RR26 | RR25 | RR24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RR23 | RR22 | RR21 | RR20 | RR19 | RR18 | RR17 | RR16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RR15 | RR14 | RR13 | RR12 | RR11 | RR10 | RR9 | RR8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RR7 | RR6 | RR5 | RR4 | RR3 | RR2 | RR1 | RR0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – RR XDMAC Channel x Read Resume
| Value | Description |
|---|---|
| 0 |
No effect |
| 1 |
The source requests for channel x are serviced by the system scheduler. |