14.9.36 XDMAC Channel x Transfer Count Status Register [x = 0..XDMAC_NB_CH-131]
| Name: | XDMAC_CTCS |
| Offset: | 0x98 + n*0x40 [n=0..31] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TC[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TC[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:0 – TC[23:0] Channel x Transfer Count
Number of bytes written by the XDMA since the last read of the Transfer Count Status register. The field does not indicate the number of bytes written to memory.
To get the number of bytes already written in memory at any time during
peripheral-to-memory transfer, use the following software procedure:
- Read the XDMAC_CTCSx.TC field to sample the number of bytes received by the XDMA.
- Perform a software flush of the channel by writing one to the XDMAC_GSWF register. This will push bytes from the internal DMA FIFO to the external memory and return an interrupt when the bytes can be read by the CPU.