14.9.31 XDMAC Channel x Block Control Register [x = 0..31]

Name: XDMAC_CBC
Offset: 0x84 + n*0x40 [n=0..31]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     BLEN[11:8] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 BLEN[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 11:0 – BLEN[11:0] Channel x Block Length

The length of the block is (BLEN+1) microblocks.