14.9.33 XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..31]

Name: XDMAC_CDS_MSP
Offset: 0x8C + n*0x40 [n=0..31]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 DDS_MSP[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DDS_MSP[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SDS_MSP[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 SDS_MSP[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:16 – DDS_MSP[15:0] Channel x Destination Data Stride or Memory Set Pattern

When XDMAC_CCx.MEMSET = 0, this field indicates the destination data stride.

Number of bytes for the data stride of channel x (two’s complement). If the field is set to zero the data is contiguous (see Data Striding Diagram).

The DDS_MSP field is only relevant when XDMAC_CCx.SAM=UBS_DS_AM.

When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern.

Bits 15:0 – SDS_MSP[15:0] Channel x Source Data Stride or Memory Set Pattern

When XDMAC_CCx.MEMSET = 0, this field indicates the source data stride.

Number of bytes for the data stride of channel x (two’s complement). If the field is set to zero the data is contiguous (see Data Striding Diagram).

The SDS_MSP field is only relevant when XDMAC_CCx.SAM=UBS_DS_AM.

When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern.