14.9.18 XDMAC Global Channel Write Resume Register
| Name: | XDMAC_GWR |
| Offset: | 0x3C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WR31 | WR30 | WR29 | WR28 | WR27 | WR26 | WR25 | WR24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WR23 | WR22 | WR21 | WR20 | WR19 | WR18 | WR17 | WR16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WR15 | WR14 | WR13 | WR12 | WR11 | WR10 | WR9 | WR8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WR7 | WR6 | WR5 | WR4 | WR3 | WR2 | WR1 | WR0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – WR XDMAC Channel x Write Resume
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
Destination requests are serviced and routed to the scheduler. |