21.5.21 Fabric Interface Control (FIC) Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:10] | Reserved | 0 | |
| [9:4] | SW_FIC_REG_SEL | 0x38 | Indicates whether a specific fabric region is accessible by FIC_0 or FIC_1. This register should not be changed during operation. 0: Fabric region associated with FIC_0 1: Fabric region associated with FIC_1 By default, fabric region 0, 1, 2 are accessible through FIC_0 and regions 3, 4, 5 are accessible through FIC_1. These bits are driven into the AHB bus in order to allocate a specific memory region to either FIC_0 or FIC_1. |
| 3 | FAB1_AHB_MODE | 0 | Controls whether the FIC_1 fabric interface supports AHB mode or APB mode. Allowed values: 0: Supports APB mode 1: Supports AHB mode |
| 2 | FAB0_AHB_MODE | 0 | Controls whether FIC_0 fabric interface supports AHB mode or APB mode. Allowed values: 0: Supports APB mode 1: Supports AHB mode |
| 1 | FAB1_AHB_BYPASS | 0 | 0: FIC_1 is configured for synchronous bridging 1: FIC_1 is configured in bypass mode, if clock ratio is 1:1 and if in AHB mode |
| 0 | FAB0_AHB_BYPASS | 0 | 0: FIC_0 is configured for synchronous bridging 1: FIC_0 is configured in bypass mode, if clock ratio is 1:1 and if in AHB mode |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.