21.5.87 MSS DDR Clock Calibration Status
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:1] | Reserved | 0 | |
| 0 | FAB_CALIB_FAIL | 0 | 0: The currently selected CCC delay values for the M3_CLK and fabric Clock are such that the FPGA fabric clock calibration circuit is running correctly. 1: The FPGA fabric clock calibration circuit is failing to operate correctly. This indicates incorrectly configured delay values for M3_CLK and/or fabric clock in the CCC. |