20.2.6.6 Reset Generation to MSS Peripherals

The Reset Controller generates block level resets for the peripherals present within the MSS. The following figure shows the block level reset generation.

The reset signal is asserted if any of the following conditions are true:

• SYSRESET_N asserted
• Block level soft reset (SOFT_RESET_CR) request asserted from the SYSREG module.

The Reset Controller can generate the reset to ENVM_0, ENVM_1(if present), ESRAM_0, ESRAM_1, Ethernet MAC, PDMA, MMUART_0, MMUART_1, SPI_0, SPI_1, I2C_0, I2C_1, TIMER, CAN (if present), HPDMA, USB OTG, COMM_BLK, FIC_0, FIC_1 (if present), MSS_GPIO (MSS_GPIO_RESET_N reset), and the FPGA fabric (MSS_RESET_N_M2F reset).