20.2.6.5 MSS GPIO Bank Resets Generator

The MSS GPIOs bank can be selectively reset through SYSREG or from Flash bits. The GPOUT register is split into four banks of one byte each and each bank has a reset signal.

The Reset Controller receives two SYSREG bits: Soft reset and Select. The Select bit determines the reset source for the associated MSS GPOUT byte. The source can be either of the following:

• Soft reset from system register
• Hard reset derived from either Power-on Reset or the GPIO_RESET_N signal from the FPGA fabric.

The GPIO_SYSRESET_SEL_CR register (defined in Table 20-4) can be configured to select one of the reset inputs. The entire GPIO bank can be kept in reset by asserting the MSS_GPIO_SOFTRESET bit in SOFT_RESET_CR (defined in Table 20-4) of SYSREG. A particular GPIO byte can be reset by asserting the corresponding MSS_GPIO_xx_xx_SOFTRESET bit in SOFT_RESET_CR (defined in Table 20-4) of SYSREG.

The generation of GPOUT bank resets for Flash bit control is shown in the following figure. Only one GPOUT byte bank reset is shown; the resets for other banks are generated in a similar way.

The Flash bits to the MSS GPIO are used to initialize the GPOUT byte on assertion of reset. When a reset is deasserted, the GPOUT byte follows the Switch Input (D). When one of the Flash bits is 
deasserted, the associated GPIO_OUT pins are initialized to "0". The following table explains the generation of GPIO_OUT. MSS_GPIO_xx_xx_DEF bits are in the MSS_GPIO_DEF register of SYSREG.