3.2.2.2 eSRAM Mapping
The cache matrix supports the ability of re-mapping eSRAM into code space. The two eSRAM blocks are re-mapped to appear at the bottom of the Cortex-M3 processor code space as shown in the following table using eSRAM Remapped mode.
| Data/Code Region | Space | Address |
|---|---|---|
| CM3 Data Region | Reserved | 0xE000_0000 to 0xFFFF_FFFF |
| DDR _SPACE 3 (256 MB) | 0xD000_0000 to 0xDFFF_FFFF | |
| DDR _SPACE 2 (256 MB) | 0xC000_0000 to 0xCFFF_FFFF | |
| DDR_ SPACE 1 (256 MB) | 0xB000_0000 to 0xBFFF_FFFF | |
| DDR _SPACE 0 (256 MB) [MIRRORED] | 0xA000_0000 to 0xAFFF_FFFF | |
| eNVM, Remap Area etc (1 GB) | 0x6000_0000 to 0x9FFF_FFFF | |
| Peripheral [SPI, UART, CAN, Fabric etc.] (0.5 GB) | 0x4000_0000 to 0x5FFF_FFFF | |
| Reserved | 0x2001_0000 to 0x3FFF_FFFF | |
| eSRAM-1 (32 KB) [MIRRORED] | 0x2000_8000 to 0x2000_FFFF | |
| eSRAM-0 (32 KB) [MIRRORED] | 0x2000_0000 to 0x2000_7FFF | |
| CM3 Code Region | DDR_SPACE 0 (256 MB) | 0x1000_0000 to 0x1FFF_FFFF |
| Reserved | 0x0018_0000 to 0x0FFF_FFFF | |
| eNVM (Remap View) [512 KB] | 0x0010_0000 to 0x0017_FFFF | |
| Reserved | 0x0001_0000 to 0x000F_FFFF | |
| eSRAM0 & eSRAM1 [64 KB] | 0x0000_0000 to 0x0000_FFFF |