3.2.2.3 DDR Mapping
In DDR Remapping, the user boot code is present in the DDR. DDR remapping is also used for debugging purposes. This can give high performance execution in systems where DDR is present. The DDR is also used as the main memory for the Cache Controller. In case the of DDR remapping, the cacheable region can be configured to 128 MB, 256 MB, or 512 MB. The Cache Controller generates the appropriate DDR address as per remap configuration settings before putting the address on the MDDR bridge.
| Data/Code Region | Space | Address |
|---|---|---|
| CM3 Data Region | Reserved | 0xE000_0000 to 0xFFFF_FFFF |
| DDR _SPACE 3 (256 MB) | 0xD000_0000 to 0xDFFF_FFFF | |
| DDR _SPACE 2 (256 MB) | 0xC000_0000 to 0xCFFF_FFFF | |
| DDR _SPACE 1 (256 MB) | 0xB000_0000 to 0xBFFF_FFFF | |
| DDR _SPACE 0 (256 MB) | 0xA000_0000 to 0xAFFF_FFFF | |
| eNVM, Remap Area etc (1 GB) | 0x6000_0000 to 0x9FFF_FFFF | |
| Peripheral [SPI, UART, CAN, Fabric etc.] (0.5 GB) | 0x4000_0000 to 0x5FFF_FFFF | |
| Reserved | 0x2001_0000 to 0x3FFF_FFFF | |
| eSRAM-1 (32 KB) | 0x2000_8000 to 0x2000_FFFF | |
| eSRAM-0 (32 KB) | 0x2000_0000 to 0x2000_7FFF | |
| CM3 Code Region | DDR_SPACE 1 (256 MB) | 0x1000_0000 to 0x1FFF_FFFF |
| DDR_SPACE 0 (256 MB) | 0x0000_0000 to 0x0FFF_FFFF |