7.2.1.2 Configuration and Status Registers

The configuration and status registers of the HPDMA controller are accessed through a 32-bit APB slave, as shown in the following figure. To enable and use HPDMA services, the AHB bus matrix master must configure the 32-bit wide descriptor registers.

HPDMA controller has four descriptors. Each descriptor has the following five registers:

  • Source memory address register
  • Destination memory address register
  • Control register
  • Status register
  • Pending Transfer register
Figure 7-3. HPDMA Registers