7.2.1.5 Read Buffer Controller

The read buffer controller places the address and asserts the ready signal to the AHB master (AHB-M1 or AHB-M2). Depending on the transfer direction, AHB-M1 or AHB-M2 initiates the data transfers from internal data buffer to the destination memory.

If the data buffer is empty or if the DMA controller pause bit is enabled, then the read buffer controller initiates IDLE transfers on the AHB bus.