7.2.1.4 Write Buffer Controller

The write buffer controller enables the appropriate AHB master (AHB-M1 or AHB-M2) to read the data from source memory. To initiate read transfers on the AHB bus, the write buffer controller provides the read address and asserts the ready signal. The AHB master acknowledges, and the write buffer controller writes the source memory data to the internal data buffer.

If the data buffer is full, the write buffer controller initiates idle transfers on the AHB bus, and asserts ready signal when at least one data buffer is available. The write buffer controller pauses the DMA transfers when the descriptor pause bit is enabled, and resumes the transfers as soon as the pause bit is disabled. When the last count value is reached, the AHB slave acknowledges the last transfer.