2.7.4 Memory Protection Unit

This section describes the Memory protection unit (MPU).

The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:

  • independent attribute settings for each region
  • overlapping regions
  • export of memory attributes to the system.

The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 processor MPU defines:

  • eight separate memory regions, 0-7
  • a background region.

When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.

The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only.

The Cortex-M3 processor MPU memory map is unified. This means instruction accesses and data accesses have same region settings.

If a program accesses a memory location that is prohibited by the MPU, the processor generates a MemManage fault. This causes a fault exception, and might cause termination of the process in an OS environment.

In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.

Configuration of MPU regions is based on memory types, see 2.5.2.1 Memory Regions, Types and Attributes.

The following table shows the possible MPU region attributes. These include shareability and cache behavior attributes that are not relevant to most microcontroller implementations. See 2.7.4.9.1 MPU Configuration for a Microcontroller for guidelines for programming such an implementation.

Table 2-70. Memory Attributes Summary
Memory Type Shareability Other Attributes Description
Strongly- ordered All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared.
Device Shared Memory-mapped peripherals that several processors share.
Non-shared Memory-mapped peripherals that only a single processor uses.
Normal Shared Non-cacheable Write-through Cacheable Write-back Cacheable Normal memory that is shared between several processors.
Non-shared Non-cacheable Write-through Cacheable Write-back Cacheable Normal memory that only a single processor uses.

Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:

Table 2-71. MPU Registers Summary
Address Name Type Required
privilege Reset
value See
0xE000ED90 MPU_TYPE RO Privileged 0x00000800 2.7.4.1 MPU Type Register
0xE000ED94 MPU_CTRL RW Privileged 0x00000000 2.7.4.2 MPU Control Register
0xE000ED98 MPU_RNR RW Privileged 0x00000000 2.7.4.3 MPU Region Number Register
0xE000ED9C MPU_RBAR RW Privileged 0x00000000 2.7.4.4 MPU Region Base Address Register
0xE000EDA0 MPU_RASR RW Privileged 0x00000000 2.7.4.5 MPU Region Attribute and Size Register
0xE000EDA4 MPU_RBAR_A1 RW Privileged 0x00000000 Alias of MPU_RBAR, see 2.7.4.4 MPU Region Base Address Register
0xE000EDA8 MPU_RASR_A1 RW Privileged 0x00000000 Alias of MPU_RASR, see 2.7.4.5 MPU Region Attribute and Size Register
0xE000EDAC MPU_RBAR_A2 RW Privileged 0x00000000 Alias of MPU_RBAR, see 2.7.4.4 MPU Region Base Address Register
0xE000EDB0 MPU_RASR_A2 RW Privileged 0x00000000 Alias of MPU_RASR, see 2.7.4.5 MPU Region Attribute and Size Register
0xE000EDB4 MPU_RBAR_A3 RW Privileged 0x00000000 Alias of MPU_RBAR, see 2.7.4.4 MPU Region Base Address Register
0xE000EDB8 MPU_RASR_A3 RW Privileged 0x00000000 Alias of MPU_RASR, see 2.7.4.5 MPU Region Attribute and Size Register